The subject matter described herein relates generally to semiconductor processing, and more particularly to wafer level alignment structures using subwavelength grating polarizers.
During semiconductor device fabrication processing numerous (e.g., hundreds of) integrated circuit chips or die, each having millions of electronic devices, may be formed on a single semiconductor wafer. The wafer may be a thin disk or round slice of semiconductor material (e.g., silicon), such as to provide a semiconductor (e.g., silicon, germanium, or a combination thereof) or semiconductor on insulator (SOI) substrate on or in which to form the electronic devices.
Similarly, targets (e.g., wafer alignment optical targets) may be formed on or in layers of the wafer to accurately align the wafers for processing to form the devices (and to form the targets). A large number of semiconductor device fabrication processing tools perform some level of basic alignment on semiconductor wafers prior to processing them. Alignment may be used to determine a radial, rotational, two dimensional, three dimensional and/or a coordinate system based position or location on the wafer. The fabrication process may include a device fabrication process to form circuit features or structures of electronic devices (e.g., to form gate structures, diffusion regions, sources,  drains, dielectric layers, gate spacers, shallow trench isolation (STI), integrated circuits, conductive interconnects, metal or alloy features, metal or alloy traces, metal or alloy contacts, and the like of transistors, resistors, capacitors and the like). The device fabrication process may include forming layers of circuitry or circuit features in or on layers of the wafer. The fabrication process may end with a dicing process to separate or “saw” the wafer into distinct chips or die. To accurately align the wafer to form the electronic device circuitry at proper locations (e.g., regions or portions of the wafer surface and/or layers below the surface), a wafer scanning (e.g., a wafer inspection or alignment) process may be used during the device fabrication process, and/or dicing process. The inspection or alignment process typically includes locating one or more optical pattern recognition targets to index the wafer.
Wafer alignment is typically accomplished by using pattern recognition software to locate specific targets, structures, or features on wafers and then correcting for wafer position relative to the tool's wafer stage. Examples of such equipment include scanner, critical dimension scanning electron microscopy (CDSEM), litho registration, defect inspection, and film thickness tools. In general, the alignment systems used on these tools are based on optical microscopes (e.g., alignment or inspection microscopes). In order for the pattern recognition to be successful, the target structures need to have sufficiently high optical contrast relative to their surrounding background. In some process technologies, targets are created by lithographically patterning large, isolated solid features (few tens of microns in size) on wafers. These pattern recognition targets are constructed from large patterns arranged in some unique shape. For some fabrication process  technologies, the large patterns may have defect issues due to line-width and/or critical dimension (CD) control requirements. For example, in some fabrication process technologies, linewidth and CD control requirements dictate very tight control of solid feature size and pattern density in order to enable the patterning process and avoid defect issues. For example, use of large, non-design rule-compliant solid features in some fabrication technologies would result in polish (e.g., chemical mechanical polishing (CMP) to planarize a surface of the wafer) dishing, film delamination, and/or defect generation, depending on the layer. These structures tend to be incompatible with such rules given that they need to be fairly large in order to be observable under an alignment microscope. 